# Quartus Prime Synthesis Tutorial

## 1.3 Quartus Prime Tutorial

For this tutorial, we will use this code for reference :

```
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY AND_GATE IS
    PORT (
        A : IN  STD_LOGIC; 
        B : IN  STD_LOGIC; 
        Y : OUT STD_LOGIC  
    );
END AND_GATE;

ARCHITECTURE Behavioral OF AND_GATE IS
BEGIN
    Y <= A AND B;
END Behavioral;
```

#### 1.3.1 Creating a New Quartus Prime Project

Create a new project by clicking new on file tab

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/U4Bimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/U4Bimage.png)

Select New Quartus Prime Project

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/1eTimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/1eTimage.png)

Select the directory where you want the project to be saved and also give the project a name and name your Top-Level Entity

#### NOTE : Remember to name your Top-Level Entity into the same name as your Top-Level entity on your .vhdl

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/BxZimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/BxZimage.png)

Choose empty project

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/mCzimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/mCzimage.png)

Add your .vhdl/.vhd file into the project

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/6zAimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/6zAimage.png)

Just select the default setting and proceed to finish

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/8CXimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/8CXimage.png)

#### 1.3.2 Synthesis Tutorial

Run the "Start Compilation" button on top bar

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/QUUimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/QUUimage.png)

Wait until the startup is finish and then go into Tools -&gt; Netlist Viewers -&gt; RTL Viewer

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/Zkrimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/Zkrimage.png)

You may see your VHDL schematic

[![image.png](https://learn.digilabdte.com/uploads/images/gallery/2025-09/scaled-1680-/hsmimage.png)](https://learn.digilabdte.com/uploads/images/gallery/2025-09/hsmimage.png)