Module 6: Looping

While Loop and For Loop

What is looping in VHDL?

A looping construct (looping statement) in VHDL is an instruction that allows a program to repeat the same block of code iteratively. In VHDL, there are two types of looping constructs: the while-loop and the for-loop.

While Loop

label_name: while (condition) loop
    -- Statements
end loop label_name;

For Loop

for index in range loop
    -- Statements
end loop;

The following are things that must be considered when using the looping construct:

While Loop

While loops operate by repeatedly checking the result of a condition. As long as this condition returns "true," the code within it will continue to execute. The looping process will end when the condition returns a "false" value. While loops are very useful when we don't have exact information about how many times the code needs to be repeated.

However, it's important to remember that there must be a method in the program to change the result of the condition from "true" to "false" so that the loop can stop. Without such a method, the program will be stuck in an infinite loop.

Here is an example of VHDL code for a Shift Register that can be modified by implementing looping.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Shift_Register is
    port (
        clk, reset: in std_logic;
        data_in: in std_logic;
        data_out: out std_logic
    );
end entity;

architecture RTL of Shift_Register is
    signal reg: std_logic_vector(7 downto 0) := (others => '0');
begin
    process (clk, reset)
    begin
        if reset = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            reg(7) <= reg(6);
            reg(6) <= reg(5);
            reg(5) <= reg(4);
            reg(4) <= reg(3);
            reg(3) <= reg(2);
            reg(2) <= reg(1);
            reg(1) <= reg(0);
            reg(0) <= data_in;
        end if;
    end process;

    data_out <= reg(7);
end architecture;

The code above still uses the regular assignment method. To implement while loop, the process in the code above can be replaced with the following code.

    process (clk, reset)
        variable i: integer := 0;
    begin
        if reset = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            while i < 8 loop
                reg(i) <= reg(i+1);
                i := i + 1;
            end loop;
        end if;
    end process;

For Loop

A for loop repeats the code within a certain range using an index variable. The code inside is executed once on each iteration. This type of looping is suitable when the number of iterations required is known in advance.

The following are things to keep in mind when using for-loops: The range to be iterated over can be defined directly or taken from another previously declared variable in the form of a vector, array, or list.

    process (clk, reset)
    begin
        if reset = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            for i in 7 downto 1 loop
                reg(i) <= reg(i-1);
            end loop;
            reg(0) <= data_in;
        end if;
    end process;

Loop Control: Next & Exit Statements

The following are two additional statements that can be used to control the looping construct:

Next

The next statement is used to skip the remaining code in the current iteration of the loop and proceed to the next iteration. In a for-loop, the index variable will be incremented or decremented automatically before the next iteration. In a while loop, this behavior depends on the logic applied. There are two ways to use the next statement.

next when (condition);
if (condition) then
    next;
end if;

Exit

The exit statement is used to stop the loop forcibly. When this statement is executed, the loop will terminate immediately, and the program will continue executing the code that follows the loop. There are two ways to use the exit statement.

exit when (condition);
if (condition) then
    exit;
end if;

Example

Below is an example of a for-loop that uses the next and exit statements.

process
    variable i: integer := 0;
begin
    for i in 0 to 7 loop
        if i = 3 then
            next; -- Skip the rest of the code in this iteration
        elsif i = 5 then
            exit; -- Exit the loop
        end if;
        reg(i) <= reg(i+1);
    end loop;
end process;

This VHDL code snippet demonstrates the use of a for-loop within a process statement. Here's the detailed explanation:

  1. Process Declaration:

    • The process block is declared, and a variable i of type integer is initialized to 0.

  2. For-Loop:

    • The for-loop iterates over the range from 0 to 7, inclusive. The loop variable i is automatically created and incremented with each iteration.

  3. Conditional Statements:

    • Inside the loop, there are two conditional checks:
      • if i = 3 then: If i equals 3, the next statement is executed. This causes the loop to skip the remaining code in the current iteration and proceed to the next iteration.
      • elsif i = 5 then: If i equals 5, the exit statement is executed. This causes the loop to terminate immediately, and the process continues with the code following the loop.

  4. Register Assignment:

    • If neither of the above conditions is met, the code reg(i) <= reg(i+1); is executed. This assigns the value of reg(i+1) to reg(i).

  5. End Loop and Process:

    • The loop ends after completing the iterations from 0 to 7 unless exited early by the exit statement.
    • The process block ends after the loop.

Summary