Module 8 : Finite State Machine

Finite State Machine

A Finite State Machine (FSM), or Finite Automata, is a mathematical model of a system whose state is capable of changing. These systems have characteristics or behaviors that vary depending on the current state. In general, FSMs are divided into two types: FSMs with output and FSMs without output.

However, in this module, only FSMs with output will be discussed. FSMs with output can be divided into 2 types, namely Mealy Machine and Moore Machine.

Mealy Machine

Mealy State Machine is an FSM in which the next state is determined by the current input and the present state. Different inputs, along with different present states, will result in different next states. For example, in digital circuits, Registers exhibit this characteristic. In everyday life, the change in state of a substance can be modeled as a Mealy State Machine.

Mealy State Machine Mealy State Machine Circuit

Moore Machine

Moore State Machine is a type of FSM where the next state is only determined by the current state, without being affected by inputs. This means that any input will not change the next state. The hallmark of a Moore State Machine is its one-way cycle structure. For example, digital circuits such as counters exhibit this property. In everyday life, the metamorphosis cycle in animals can be modeled as a Moore State Machine.

Moore State Machine Moore State Machine Circuit

Finite State Machine in VHDL

Basically, FSM serves to describe the workings of a sequential circuit. Therefore, the VHDL code of an FSM is not much different from the VHDL code of an ordinary sequential circuit, which uses a process statement (behavioral model). There are many methods that can be used to create an FSM using VHDL. However, we will only learn the most basic method. The method requires a minimum of two processes, commonly called Synchronous Process and Combinatorial Process.

Finite State Machine

FSM Implementation Example in VHDL

Moore Machine

This FSM has two states: ST0 and ST1. In the ST0 state, the FSM outputs '0', and in ST1, the output is '1'. This FSM also accepts two inputs: CLR and TOG_EN. The CLR input returns the FSM to ST0, while TOG_EN determines whether the FSM can switch states.

Moore Machine 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FSM_Moore is
    Port ( CLK : in STD_LOGIC;
           CLR : in STD_LOGIC;
           TOG_EN : in STD_LOGIC;
           Z1 : out STD_LOGIC);
end FSM_Moore;

architecture Behavioral of FSM_Moore is
    type state_type is (ST0, ST1);
    signal state, next_state : state_type;
begin
    process (CLK, CLR)
    begin
        if CLR = '1' then
            state <= ST0;
        elsif rising_edge(CLK) then
            state <= next_state;
        end if;
    end process;

    process (state, TOG_EN)
    begin
        case state is
            when ST0 =>
                if TOG_EN = '1' then
                    next_state <= ST1;
                else
                    next_state <= ST0;
                end if;
            when ST1 =>
                if TOG_EN = '1' then
                    next_state <= ST0;
                else
                    next_state <= ST1;
                end if;
        end case;
    end process;

    process (state)
    begin
        case state is
            when ST0 =>
                Z1 <= '0';
            when ST1 =>
                Z1 <= '1';
        end case;
    end process;
end Behavioral;

Penjelasan Kode

Mealy Machine

This FSM has three states: “00”, ‘01’, and ‘11’. In addition, this FSM accepts two inputs: SET and X. The SET input returns the FSM to state “11”, while X determines the next output and state

Mealy Machine 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FSM_Mealy is
    Port ( CLK : in STD_LOGIC;
           SET : in STD_LOGIC;
           X : in STD_LOGIC;
           Y : out STD_LOGIC_VECTOR (1 downto 0);
           Z2 : out STD_LOGIC);
end FSM_Mealy;

architecture Behavioral of FSM_Mealy is
    type state_type is (ST00, ST01, ST11);
    signal state, next_state : state_type;
begin
    process (CLK, SET)
    begin
        if SET = '1' then
            state <= ST11;
        elsif rising_edge(CLK) then
            state <= next_state;
        end if;
    end process;

    process (state, X)
    begin
        case state is
            when ST00 =>
                if X = '0' then
                    next_state <= ST00;
                else
                    next_state <= ST01;
                end if;
            when ST01 =>
                if X = '0' then
                    next_state <= ST00;
                else
                    next_state <= ST11;
                end if;
            when ST11 =>
                next_state <= ST11;
        end case;
    end process;

    process (state, X)
    begin
        case state is
            when ST00 =>
                Y <= "00";
                Z2 <= '0';
            when ST01 =>
                Y <= "01";
                Z2 <= '1';
            when ST11 =>
                Y <= "11";
                Z2 <= X;
        end case;
    end process;
end Behavioral;

Penjelasan Kode