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Realtime System & IoT
Digital System Design
Fundamentals of Digital Systems
Module 4 : Software Timers & Interrupts
Module 5 : Deadlock & Multicore Systems
Module 9 : Mesh
Tutorials
Module 4: Testbench
Module 5: Structural Style Programming In VHDL
Module 4 : Complex Logic Gates
Learning Objective:1. Understand the principle of complex logic gates.2. Understand NAND and NOR gates as universal gates.
Module 1: Introduction to RTOS & Task Scheduling
Learning Objectives Understand the fundamentals of Real-Time Operating Systems (RTOS). Explore the basics of task scheduling and prioritization. Learn how to create and manage tasks using RTOS APIs. Understand the role of tick interrupts in task scheduli...
Module 2: Memory Management & Queue
Learning Objective: Understand ESP32 Memory Structure Comprehend the Challenges of Memory Management Explore FreeRTOS Memory Management Techniques Implement Dynamic Memory Allocation Handle Memory Issues in Embedded Systems Understand Task Synchronizat...
Module 6: Looping
Module 7: Procedure, Function, and Impure Function
Module 7 : Digital Arithmetic Circuit
Learning Objective: 1. Understand basic digital arithmetic using adder and subtractor.
Module 8 : Flip-Flop and Latch
Learning Objectives: 1. Understand the working principles of sequential circuits.2. Understand the differences between sequential circuits and combinatorialcircuits.3. Understand how latches and flip-flops work as the base component thatcompose sequential cir...
Module 9 : Register and Counter
Learning Objectives: Understand the concept of parallel and serial binary operations Understand a combination and conversion of parallel and binary operations
Module 5 : Decoder & Encoder
Learning Objectives :1. Understand the working principles of decoders and encoders. 2. Being able to distinguish between a decoder and an encoder, as well as knowing when to use each one
Module 6 : Multiplexer & Demultiplexer
Learning Objectives :1. Understand how Multiplexer and Demultiplexer works. 2. Being able to distinguish between a Multiplexer and a Demultiplexer as well as knowing when to use each one.
Module 6 : Bluetooth
Modul 10: LoRa
Module 8 : Finite State Machine
Module 7 : WiFi, HTTP, and MQTT
Module 4 : Software Timers & Interrupts
Software Timer Software timer is a feature of FreeRTOS that can call a function when the timer expires. This function is known as a callback function and is passed to the timer as an argument. The callback function must be quick and non-blocking, similar to an...
Module 5 : Deadlock & Multicore Systems
Deadlock: Understanding and Prevention Deadlock is a situation where two or more processes or tasks are indefinitely blocked, waiting for each other to release some resources needed to proceed. Deadlock can occur in any system involving concurrency and resourc...
Module 9 : Mesh
Mesh Concept A mesh network is a type of network topology where devices, called nodes, are interconnected, allowing data to be transmitted between them even if some nodes are out of direct range of each other. This creates a robust and self-healing network whe...
PlatformIO (Recommended)
About PlatformIO is a versatile, open-source ecosystem designed for embedded development, providing a unified platform for building, managing, and debugging firmware across a wide range of microcontroller architectures. Integrated with popular IDEs like VSCode...
Testbench and Port Mapping
Testbench In VHDL, a testbench is a module that instantiates the unit under test (UUT) and applies stimulus to it. The stimulus can be a set of input signals, a clock signal, or a reset signal. The testbench also monitors the output signals of the UUT and comp...
Testbench in Combinational Circuit
To use a testbench in a combinational circuit, you need to follow these steps: 1. We must have a VHDL code that to be tested. library ieee; use ieee.std_logic_1164.all; entity UUT is port ( input_signal1 : in std_logic; input_signal2 : in ...
Testbench Architecture Models, Assert, and Report
Testbench Architecture Models As mentioned in the previous section, there are threen main testbench architecture models: Simple Testbench Works for simple designs with a few inputs and outputs. Values are applied to the inputs, and the outputs are monitored. E...
Testbench for Sequential Circuit
Sequential circuit testbenches are similar to those for combinational circuits but include additional inputs like Clock and Reset. Clock signals require a separate process statement, while the reset signal can be configured as needed. library ieee; use ieee.s...
Read and Write File
In VHDL, you can read and write files using the textio package. The textio package provides procedures and functions for reading and writing text files. You can use the textio package to read data from a file into a variable or write data from a variable to a ...
External Reference
Check out the external reference by digikey: Software Timers & Hardware Interrupts
Structural Style, Port Mapping, and Generic Map
Structural Style Programming Structural Style Programming in VHDL allows designers to build digital circuits using basic components connected to form a more complex system. In this approach, circuits are represented as collections of entities connected in a sp...
VHDL Modularity
We will build a 4-bit Ripple Carry Adder using 4 Full Adders in Structural Style Programming. Each Full Adder's carry-out serves as the carry-in for the next Full Adder, creating a ripple effect in addition. Step 1 - Full Adder Entity Inside full adder entity,...
Array and Types in VHDL
Array In VHDL, an array is a collection of elements that have the same data type. You can think of an array as a variable that has many elements with the same data type, and these elements are indexed for access. The index can be a number or another indexable ...
Theory
Complex Logic Gates: Theory Introduction Complex logic gates are formed by combining basic logic gates like AND, OR, and NOT to create more advanced circuits that perform specific logical functions. These gates simplify digital circuit design and can reduce th...
External Reference
Check out the external reference by digikey: Deadlock & Multicore
Module 1: Introduction to RTOS & Task Scheduling
Understanding Real-Time Operating Systems (RTOS) A Real-Time Operating System (RTOS) is a type of operating system designed to meet the time constraints of real-time applications. Real-time applications are those that have strict time limits for completing the...
Code Sample
/** * FreeRTOS LED Demo * * One task flashes an LED at a rate specified by a value set in another task. * * Date: December 4, 2020 * Author: Shawn Hymel * License: 0BSD */ // Needed for atoi() #include <stdlib.h> // Use only core 1 for demo purposes ...
Module 2: Memory Management & Queue
Memory Management in ESP32 Memory management is a crucial aspect of developing embedded systems, especially for platforms with limited resources like the ESP32. The ESP32 is a dual-core microcontroller that supports various wireless protocols, such as Wi-Fi, B...
Code Sample
This example demonstrates a simple FreeRTOS queue communication between two tasks (Task1 and Task2) running on an ESP32. Here's how it works: Task1: This task generates a random integer between 0 and 100, dynamically allocates memory for it using pvPortMallo...
While Loop and For Loop
What is looping in VHDL? A looping construct (looping statement) in VHDL is an instruction that allows a program to repeat the same block of code iteratively. In VHDL, there are two types of looping constructs: the while-loop and the for-loop. While Loop label...