Digital System Design

Module 4: Testbench

Testbench and Port Mapping

Testbench In VHDL, a testbench is a module that instantiates the unit under test (UUT) and applie...

Testbench in Combinational Circuit

To use a testbench in a combinational circuit, you need to follow these steps: 1. We must have a ...

Testbench Architecture Models, Assert, and Report

Testbench Architecture Models As mentioned in the previous section, there are threen main testben...

Testbench for Sequential Circuit

Sequential circuit testbenches are similar to those for combinational circuits but include additi...

Read and Write File

In VHDL, you can read and write files using the textio package. The textio package provides proce...

Module 5: Structural Style Programming In VHDL

Structural Style, Port Mapping, and Generic Map

Structural Style Programming Structural Style Programming in VHDL allows designers to build digit...

VHDL Modularity

We will build a 4-bit Ripple Carry Adder using 4 Full Adders in Structural Style Programming. Eac...

Array and Types in VHDL

Array In VHDL, an array is a collection of elements that have the same data type. You can think o...

Module 6: Looping

While Loop and For Loop

What is looping in VHDL? A looping construct (looping statement) in VHDL is an instruction that a...

Loop Control: Next & Exit Statements

The following are two additional statements that can be used to control the looping construct: Ne...

Module 7: Procedure, Function, and Impure Function

Procedure and Function

Procedure in VHDL In VHDL, a "procedure" is a language construct used to group multiple statement...

Procedure, Function, and Impure Function Synthesis

In VHDL, both "functions" and "procedures" can be used in the description of hardware. However, i...

Module 8 : Finite State Machine

Finite State Machine

A Finite State Machine (FSM), or Finite Automata, is a mathematical model of a system whose state...

Finite State Machine in VHDL

Basically, FSM serves to describe the workings of a sequential circuit. Therefore, the VHDL code ...

FSM Implementation Example in VHDL

Moore Machine This FSM has two states: ST0 and ST1. In the ST0 state, the FSM outputs '0', and in...

Module 9 : Microprogramming

Microprogramming in VHDL

Microprogramming in VHDL Microprogramming is a technique in computer design that involves using m...

Final Project Digital System Design

Selamat! Anda sudah hampir menyelesaikan praktikum Perancangan Sistem Digital. Pada modul terakhi...