Digital System Design
Module 4: Testbench
Intro, Types, and Port Mapping
Introduction In VHDL, a testbench is a module that instantiates the unit under test (UUT) and app...
Testbench, Assert, and Report
Testbench in Combinational Circuit To use a testbench in a combinational circuit, you need to fol...
File Operations
Read and Write File In VHDL, you can read and write files using the textio package. The textio pa...
Module 5: Structural Style Programming In VHDL
Structural Style, Port Mapping, and Generic Map
Structural Style Programming Structural Style Programming in VHDL allows designers to build digit...
VHDL Modularity
We will build a 4-bit Ripple Carry Adder using 4 Full Adders in Structural Style Programming. Eac...
Array and Types in VHDL
Array In VHDL, an array is a collection of elements that have the same data type. You can think o...
Module 6: Looping
Module 7: Procedure, Function, and Impure Function
Procedure and Function
Procedure in VHDL In VHDL, a "procedure" is a language construct used to group multiple statement...
Procedure, Function, and Impure Function Synthesis
In VHDL, both "functions" and "procedures" can be used in the description of hardware. However, i...
Example
Procedure library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Adder is port ( A, B: in...