Module 4 - Testbench
1. Understanding Testbench in VHDL
A VHDL testbench is a non-synthesizable VHDL entity used to simulate and verify the functionality...
2. Components of a Testbench
2.1 Entity Declaration The testbench entity is declared without any ports. It's a self-contained ...
3. Testbench Architecture Models
3.1 Testbench for Combinational Circuit There are three architectural models for changing the val...
4. Assert and Report Statement
4.1 Assert Statement The assert statement is used for creating self-checking testbenches. It acts...
5. File I/O in VHDL
In VHDL, we can perform file handling using the TextIO library. This feature is very useful for d...
Extra: Array in VHDL
6.1 Array In VHDL, an array is a collection of elements that share the same data type. You can th...