7. ADC Conversion Flowchart

Here is the complete workflow for using the ADC on the ATmega328p:

The flowchart above illustrates the ADC reading process on the ATmega328p in single conversion mode using the polling method, with the following configuration:

1. Conversion Mode: The ADC operates in single conversion mode, meaning each conversion starts manually by setting the ADSC = 1 bit.

2. Synchronization Method: The conversion completion status is checked using polling of the ADIF bit in the ADCSRA register, instead of using interrupts.

3. Auto Trigger: This flowchart assumes ADATE = 0, so conversions do not run automatically and must be restarted by the program each time a reading is taken.

4. ADC Interrupt: This flowchart does not use ADC interrupts, so ADIE = 0.

5. Input Channel: The configuration example in the flowchart uses ADC0 (pin A0 / PC0) as the analog input channel.

6. Reference Voltage: This flowchart follows an assembly program example that uses the internal reference voltage via the configuration of the REFS1:REFS0 bits in the ADMUX register.

7. Conversion Data Format: The ADC result is stored in right-justified format (ADLAR = 0), so the full 10-bit value is read through two registers:

   • ADCL as the low-byte
   • ADCH as the high-byte

8. Data Register Reading Order: The ADCL register must be read first, followed by ADCH, to ensure the conversion data remains consistent.

9. ADC Prescaler: This example uses a CLK/128 prescaler (ADPS2:ADPS0 = 111). If the system clock is 16 MHz, the ADC clock becomes:

   

   This value is within the recommended ADC operating range.

Summary of Configuration Used

• ADC Mode: Single Conversion
• Trigger Mode: Manual (ADSC = 1)
• Polling / Interrupt: Polling (ADIF)
• Auto Trigger: Disabled (ADATE = 0)
• Interrupt ADC: Disabled (ADIE = 0)
• Channel: ADC0 / A0 / PC0
• Data Alignment: Right-justified (ADLAR = 0)
• Prescaler: CLK/128
• ADC Clock: 125 kHz (if F_CPU = 16 MHz)